Example embodiments of the present invention relate to a semiconductor memory device and a refresh method thereof, which can reduce current consumption when performing a self-refresh operation.
Recently, as demand for mobile products such as mobile phones and PDAs (personal digital assistant) abruptly increases, efforts have been made to reduce current consumption of DRAM (dynamic random access memory) mounted in these mobile products.
In a DRAM, unlike an SRAM (static random access memory) or a flash memory, a phenomenon occurs in which the data stored in a memory cell disappears with a lapse of time. In order to prevent an occurrence of such a phenomenon, an operation for recovering the data stored in a memory cell from an outside source every preset cycle is needed. Such an operation is called a refresh operation. Refresh is implemented in such a way as to sense and amplify data by selecting a word line for refreshing at least one time within a retention time of memory cells arranged in a bank. The retention time means a time for which data can be retained in a cell without performing refresh after the data is stored in the cell.
Refresh is divided into an auto-refresh which is performed in a normal mode and a self-refresh which is performed in a power-down mode. In general, since the self-refresh is performed in the power-down mode, it has a longer cycle than the auto-refresh.
FIG. 1 is a block diagram illustrating a configuration of a conventional semiconductor memory device.
The conventional semiconductor memory device includes a command decoder 11, a self-refresh pulse generation unit 12, an access signal generation unit 13, and a memory core 14.
The command decoder 11 decodes a command signal CMD and a clock enable signal CKE and generates a self-refresh signal SREF and an auto-refresh pulse AREFPB. The command signal CMD includes a chip selection signal (/CS), a RAS signal (/RAS), a CAS signal (/CAS) and a write enable signal (/WE). The command decoder 11 decodes the chip selection signal (/CS), the RAS signal (/RAS), the CAS signal (/CAS) and the write enable signal (/WE) and generates the self-refresh signal SREF before toggling of a clock (CLK) is stopped after the clock enable signal CKE is disabled. The self-refresh signal SREF is enabled to a logic high level when performing a self-refresh operation. The auto-refresh pulse AREFPB includes a pulse which is cyclically generated when performing an auto-refresh operation.
The self-refresh pulse generation unit 12 generates a self-refresh pulse SREFPB in response to the self-refresh signal SREF. The self-refresh pulse SREFPB includes a pulse which is cyclically generated when performing the self-refresh operation.
The access signal generation unit 13 counts row addresses XADD<1:5> one bit by one bit and outputs the counted bits of the row addresses XADD<1:5> to the memory core 14. Also, the access signal generation unit 13 outputs first to fourth bank active signals XACT<1:4> simultaneously to the memory core 14 in response to the self-refresh pulse SREFPB when performing the self-refresh operation, and outputs the first to fourth bank active signals XACT<1:4> simultaneously to the memory core 14 in response to the auto-refresh pulse AREFPB when performing the auto-refresh operation.
The memory core 14 includes first to fourth banks 141 to 144. The memory core 14 selects a word line by the row addresses XADD<1:5> while simultaneously activating the first to fourth banks 141 to 144 by the first to fourth bank active signals XACT<1:4> and performs a refresh operation for the memory cells connected with a word line.
Current consumption increases in the conventional semiconductor memory device because, the word line is selected by the row addresses XADD<1:5> while simultaneously activating the first to fourth banks 141 to 144; and the refresh operation is performed for the memory cells connected with the word line when performing not only the auto-refresh operation but also the self-refresh operation with a longer refresh cycle.